Signed-off-by: Dmitry Petrov <dpetrov@dev.rtsoft.ru>

Yadviga Grigoryeva authored Oct 06, 2020 and Dmitry Petrov committed Oct 06, 2020

Fot dcss graphics input IMX8MQ_VIDEO_PLL1_REF_SEL is added
to mipi dsi clocks and its parent is set to 27mhz osc.
Otherwise it was set to 25mhz and caused glmark2 flickering
on single-channel lvds panel ampire am-1280800n4tzqw-t03h.
IMX8MQ_VIDEO_PLL1_REF_SEL already is set to 27Mhz for lcdif input.

Yadviga Grigoryeva authored Oct 01, 2020 and Dmitry Petrov committed Oct 02, 2020

I had to move ti_sn_bridge_configure from bridge_pre_enable to bridge_enable call
and add setting gpio EN to HIGH to ti_sn_bridge_configure before internal bridge's reset.
This makes possible to set gpio EN to HIGH when mipi dsi clock is already run after 10ms delay.
Sequence of running bridges routines: lvds pre-enable, mipi dsi pre-enable, lvds enable, mipi dsi enable. Mipi clocks are set in mipi dsi pre-enable routine.

Richard Liu authored Sep 01, 2020 and Edgar Cherkasov committed Oct 01, 2020

There is kernel panic when stop android or kill surfaceflinger
after enable framebuffer tile compression on 8mq board.
The root cause of the issue is dcss driver not api to receive
ts fd, gpu driver will set the ts_dma_buf in _SetVidMemMetadata(),
dcss driver get the ts buffer physical address from ts_dma_buf,
when stop android framebuffer and matched ts buffer will free,
previous ts_dma_buf get from ts_fd will be invalid, when dcss
driver use this ts_dma_buf will cause problem. It is a common
issue, if Linux Weston do the similar stop should also meet
the same panic issue.

Keep a reference for ts_dma_buf in _SetVidMemMetadata(),
decrease the reference in _dmabuf_release() can avoid the
panic issue.

Kernel panic log:
[   41.007431] kernel BUG at drivers/gpu/drm/drm_gem.c:154!
[   41.139375] Call trace:
[   41.141824]  drm_gem_object_init+0xb8/0xbc
[   41.145920]  drm_gem_cma_prime_import_sg_table+0x84/0xdc
[   41.151233]  drm_gem_prime_import_dev+0xe8/0x194
[   41.160036]  dcss_plane_atomic_set_base+0x31c/0x3d0
[   41.164915]  dcss_plane_atomic_update+0x450/0x46c
[   41.164923]  drm_atomic_helper_commit_planes+0x130/0x31c
[   41.182255]  dcss_drm_atomic_commit_tail+0xcc/0x150
[   41.187139]  dcss_commit_work+0x10/0x1c
[   41.197322]  process_one_work+0x2d8/0x580
[   41.201333]  worker_thread+0x28c/0x518
[   41.205085]  kthread+0x14c/0x15c
[   41.208316]  ret_from_fork+0x10/0x18

Change-Id: I385851b436d1fead1131ce25f496bdd5d3d14264
Signed-off-by: Richard Liu <xuegang.liu@nxp.com>
(cherry picked from commit 9ef46bda523088bfba51b7432acd2c1e21e547d5)

Richard Liu authored Aug 26, 2020 and Edgar Cherkasov committed Oct 01, 2020

Android pass ts_address to dcss to fix kernel panic issue
reported in ticket MA-12928, this fix solution is not formal.
Remove ts_address code to keep align with Linux, if android
still meet panic issue for corner case we need check root
cause and do formal fix.

Change-Id: I04a6294f237e0c1ed5544dce1dc13e5a6ac232ab
Signed-off-by: Richard Liu <xuegang.liu@nxp.com>
(cherry picked from commit 54baa89690f61101c8182cd4fed2177941476587)

Add dcss_crtc_atomic_check into dcss_helper_funcs, otherwise
CRTC will not be disabled after eDP plug out.

As result DSI bridge will not be disabled and after eDP plug in
there are no picture on display.

DSI brifge (nwl-dsi) must be disabled, otherwise DSI data will
not be handled properly by DSI-to-eDP sn65dsi86 bridge.

dcss_crtc_atomic_check call in the same manner as drm_simple_kms_crtc_check.

Soft-resetting the chip by SOFT_RESET (0x09) register if
LOSS_OF_DP_SYNC_LOCK_ERR error has been occured.

It fixes the occasional "no image" issue after display hot plug.

Setting VSTREAM_ENABLE after drm_panel_enable with 500ms delay
to reduce the amount of LOSS_OF_DP_SYNC_LOCK errors.

This error is supposed to occur due to race condition between
sn65dsi86 bridge and nwl-dsi drivers.

In addition, the error occurs only after reconnection of the DP
display, first connect does not cause this error.

Delay length was determined by experiments with AOC I2475PXQU display.

On i.MX8M* the snvs clock is mandatory cf. DT binding doc, add it.

git.kernel.org/linux-stable/linux-5.8.y
commit f58dcab68aa57e74c12c9bec7ff1bb73e0b35143

This will prevent sporadic problem when tpm device failed
to startup properly.

Edgar Cherkasov authored Sep 07, 2020 and Dmitry Petrov committed Sep 08, 2020

Add irq for edp bridge and disable irq for sn65dsi86 bridge
due to its not routed to soc on real hardware.

Edgar Cherkasov authored Aug 24, 2020 and Dmitry Petrov committed Sep 08, 2020

Enabling HPD during bridge_pre_enable with 100ms delay.
It prevents possible "no picture on display" during cold boot.

Edgar Cherkasov authored Aug 24, 2020 and Dmitry Petrov committed Sep 08, 2020

Taken from sAMX8X, original commint message:

Those fix has been lost during moving from 4.19 to 5.4.
Original fix commit 487d5194f3557a8b753265f738aa88a552cb80da.

Douglas Anderson authored May 18, 2020 and Dmitry Petrov committed Sep 08, 2020

The ti-sn65dsi86 MIPI DSI to eDP bridge chip supports arbitrary
remapping of eDP lanes and also polarity inversion.  Both of these
features have been described in the device tree bindings for the
device since the beginning but were never implemented in the driver.
Implement both of them.

Part of this change also allows you to (via the same device tree
bindings) specify to use fewer than the max number of DP lanes that
the panel reports.  This could be useful if your display supports more
lanes but only a few are hooked up on your board.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200518114656.REPOST.v2.1.Ibc8eeddcee94984a608d6900b46f9ffde4045da4@changeid

All supported OPPs are listed in parent device tree

Mikhail Vanyulin authored Jun 08, 2020 and Dmitry Petrov committed Aug 14, 2020

Signed-off-by: Mikhail Vanyulin <mvanyulin@dev.rtsoft.ru>