- LPDDR4 manual de-rate workaround set to Option 2 for 4 GiB
  and 2 GiB memory variants.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>

- use the lpddr4_timing.c file generated by DDR stress test
  tool for board specific lpddr4 timing settings.
- use NXP LPDDR4 driver located in drivers/ddr/imx/imx8m by
  enabling the IMX8M_LPDDR4 configuration setting.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>

Update the board codes to use latest DDR script and support flexspi boot,
USB host/gadget, etc.
Also add DDR4 EVK board support for RAW NAND boot.
Signed-off-by: Ye Li <ye.li@nxp.com>

Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UART
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.

The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
PMIC:  PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE:  Configureing TZASC380
NOTICE:  BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty
NOTICE:  BL31: Built : 09:28:54, Nov  8 2018
lpddr4 swffc start
NOTICE:  sip svc init

U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)

CPU:   Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM:  3 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 using MAC address from ROM
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>