Commit f0c3a52a authored by Thomas Schäfer's avatar Thomas Schäfer
Browse files

pitx-imx8m: fix eth0 support



- add workaround in dts that allows TI DP83867 PHY configs to
  be read from driver.
- enable GBE0_PWDN#
Signed-off-by: Thomas Schäfer's avatarThomas Schaefer <thomas.schaefer@kontron.com>
parent bc388b3f
......@@ -73,7 +73,7 @@
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
>;
};
......@@ -259,20 +259,30 @@
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
phy-reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
fsl,magic-packet;
status = "okay";
/* START of DP83867 patch for U-Boot */
/*
* For some unknown reasons, DP83867 PHY driver for U-Boot doesn't
* read its properties from the phy0 node.
* As a workaround, we move them here
*/
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk = <1>;
/* END of DP83867 patch for U-Boot */
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ti,dp83867", "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
// ti,dp83867-rxctrl-strap-quirk;
// ti,min-output-impedance;
};
};
};
......
......@@ -141,14 +141,14 @@ static void setup_iomux_fec(void)
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
return set_clk_enet(ENET_125MHZ);
}
......@@ -164,6 +164,7 @@ int board_phy_config(struct phy_device *phydev)
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
......@@ -415,6 +416,7 @@ static iomux_v3_cfg_t const gpio_pads[] = {
IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int misc_init_r(void)
......@@ -432,7 +434,7 @@ int misc_init_r(void)
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
gpio_request(IMX_GPIO_NR(3, 5), "GPIO0");
gpio_direction_output(IMX_GPIO_NR(3,5), 0); /*GPIO0*/
gpio_direction_output(IMX_GPIO_NR(3,5), 0); /*GPIO0*/
gpio_request(IMX_GPIO_NR(3, 15), "GPIO1");
gpio_direction_output(IMX_GPIO_NR(3,15), 0); /*GPIO1*/
gpio_request(IMX_GPIO_NR(3, 17), "GPIO2");
......@@ -449,7 +451,10 @@ int misc_init_r(void)
gpio_direction_output(IMX_GPIO_NR(3,12), 0); /*GPIO7*/
gpio_request(IMX_GPIO_NR(1, 5), "CAM_RST#");
gpio_direction_output(IMX_GPIO_NR(1,5), 1); /*CAM0_RST# */
gpio_direction_output(IMX_GPIO_NR(1,5), 1); /*CAM0_RST#*/
gpio_request(IMX_GPIO_NR(1, 10), "GBE0_PWDN#");
gpio_direction_output(IMX_GPIO_NR(1,10), 1); /*GBE0_PWDN*/
return 0;
}
......
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