Commit de868045 authored by Thomas Schäfer's avatar Thomas Schäfer
Browse files

pitx-imx8m: move SPI_FLASH settings to defconfig



- move settings from include/configs to defconfig
- remove uncommented settings from config
- adapt qspi node in dts
Signed-off-by: Thomas Schäfer's avatarThomas Schaefer <thomas.schaefer@kontron.com>
parent 36495706
......@@ -434,8 +434,8 @@
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "macronix,mx25l25635e";
spi-max-frequency = <30000000>;
compatible = "macronix,mx25l25635e", "spi-flash";
spi-max-frequency = <20000000>;
spi-nor,ddr-quad-read-dummy = <6>;
};
};
......
......@@ -18,6 +18,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
......@@ -41,7 +42,11 @@ CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=20000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
......@@ -53,7 +58,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPI_MEM=y
CONFIG_FSL_QSPI=y
CONFIG_DM_THERMAL=y
CONFIG_NXP_TMU=y
CONFIG_USB=y
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Kontron Asia Pacific Design.
*
* SPDX-License-Identifier: GPL-2.0+
* (C) Copyright 2019
* Kontron Asia Pacific Design
* (C) Copyright 2020
* Thomas Schaefer, Kontron Europe GmbH
* thomas.schaefer@kontron.com
*/
#ifndef __PITX_IMX8M_H
......@@ -32,33 +35,15 @@
#define CONFIG_EMB_EEP_I2C_EEPROM_BUS_NUM_EE1 0
#define CONFIG_EMB_EEP_I2C_EEPROM_ADDR_LEN_1 2
#define CONFIG_EMB_EEP_I2C_EEPROM_ADDR_1 0x50
#define CONFIG_EMB_EEP_I2C_EEPROM_OFFSET_1 0x0
#define CONFIG_EMB_EEP_I2C_EEPROM_SIZE 0x1000
#define CONFIG_EMB_EEP_I2C_EEPROM_ADDR_1 0x51
#define CONFIG_EMB_EEP_I2C_EEPROM_OFFSET_1 0x0
#define CONFIG_EMB_EEP_I2C_EEPROM_SIZE 0x1000
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define D_ETHADDR "02:00:00:01:00:44"
#define D_ETH1ADDR "02:00:00:01:00:45"
/******************************************************************************
* I2C Configs
*/
/*#undef CONFIG_DM_I2C
#define CONFIG_SYS_I2C*/
#endif
#if 0
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_MXC_I2C1_SPEED 100000
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_MXC_I2C2_SPEED 100000
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_MXC_I2C3_SPEED 100000
#endif
/******************************************************************************/
......@@ -230,8 +215,9 @@
#define PHYS_SDRAM_2 0x100000000UL
#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1GB DDR in DRAM2 region */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(PHYS_SDRAM_SIZE >> 1))
#define CONFIG_BAUDRATE 115200
......@@ -239,12 +225,10 @@
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
/* Monitor Command Prompt */
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "u-boot=> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
......@@ -260,23 +244,8 @@
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_SPI_FLASH_BAR
#if 0
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
#define FSL_QSPI_FLASH_SIZE (SZ_32M)
#define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE (SZ_16M)
#endif
#define CONFIG_MXC_GPIO
......
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