Commit b66b948b authored by Thomas Schäfer's avatar Thomas Schäfer
Browse files

pitx-imx8m: support additional BRD_REV GPIOs



- Add BRD_REV[3:5] GPIOs to support memory variants and later board
  revisions.
- Add pitx_gpio_t struct for cleaner gpio init and request in
  'board_gpio_init' function.
Signed-off-by: Thomas Schäfer's avatarThomas Schaefer <thomas.schaefer@kontron.com>
parent 120d4c0e
...@@ -44,14 +44,10 @@ extern int EMB_EEP_I2C_EEPROM_BUS_NUM_1; ...@@ -44,14 +44,10 @@ extern int EMB_EEP_I2C_EEPROM_BUS_NUM_1;
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
static const char *hw_variants[8] = { static const char *hw_variants[4] = {
"unknown", "reserved",
"unknown", "reserved",
"unknown",
"L130", "L130",
"L140",
"L150",
"L160",
"L120" "L120"
}; };
...@@ -93,6 +89,72 @@ static iomux_v3_cfg_t const uart_pads[] = { ...@@ -93,6 +89,72 @@ static iomux_v3_cfg_t const uart_pads[] = {
IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
}; };
#define BRD_REV_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_FSEL2 | PAD_CTL_DSE7)
static iomux_v3_cfg_t const gpio_pads[] = {
IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
};
struct pitx_gpio_t pitx_gpios[] = {
{ "GPIO00", IMX_GPIO_NR(3, 5), 1, 1 },
{ "GPIO01", IMX_GPIO_NR(3, 15), 1, 1 },
{ "GPIO02", IMX_GPIO_NR(3, 17), 1, 1 },
{ "GPIO03", IMX_GPIO_NR(3, 18), 1, 1 },
{ "GPIO04", IMX_GPIO_NR(3, 16), 1, 1 },
{ "GPIO05", IMX_GPIO_NR(3, 10), 1, 1 },
{ "GPIO06", IMX_GPIO_NR(3, 11), 1, 1 },
{ "GPIO07", IMX_GPIO_NR(3, 12), 1, 1 },
{ "LVDS_VDD_EN", IMX_GPIO_NR(5, 6), 1, 1 },
{ "DSI_RST#", IMX_GPIO_NR(3, 20), 1, 1 },
{ "CAM_RST#", IMX_GPIO_NR(1, 5), 1, 1 },
{ "GBE0_PWDN#", IMX_GPIO_NR(1, 10), 1, 1 },
{ "BRD_REV0", IMX_GPIO_NR(5, 0), 0, 0 },
{ "BRD_REV1", IMX_GPIO_NR(5, 1), 0, 0 },
{ "BRD_REV2", IMX_GPIO_NR(5, 2), 0, 0 },
{ "BRD_REV3", IMX_GPIO_NR(4, 0), 0, 0 },
{ "BRD_REV4", IMX_GPIO_NR(4, 11), 0, 0 },
{ "BRD_REV5", IMX_GPIO_NR(4, 20), 0, 0 },
};
int board_gpio_init(void)
{
int i;
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
for (i=0 ; i<ARRAY_SIZE(pitx_gpios) ; i++) {
int gpio = pitx_gpios[i].gpio;
int outval = pitx_gpios[i].outval;
gpio_request(gpio, pitx_gpios[i].label);
if (pitx_gpios[i].inout)
gpio_direction_output(gpio, outval);
else
gpio_direction_input(gpio);
}
return 0;
}
int board_early_init_f(void) int board_early_init_f(void)
{ {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
...@@ -402,69 +464,8 @@ uint64_t getBootCounter (int eeprom_num) ...@@ -402,69 +464,8 @@ uint64_t getBootCounter (int eeprom_num)
static int get_hw_rev(void) static int get_hw_rev(void)
{ {
return ((gpio_get_value(IMX_GPIO_NR(5,0)) | return ((gpio_get_value(IMX_GPIO_NR(5, 2)) |
gpio_get_value(IMX_GPIO_NR(5,1)) << 1 | gpio_get_value(IMX_GPIO_NR(4, 0)) << 1 ) & 0x3 );
gpio_get_value(IMX_GPIO_NR(5,2)) << 2 ) & 0x7 );
}
#define BRD_REV_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_FSEL2 | PAD_CTL_DSE7)
static iomux_v3_cfg_t const gpio_pads[] = {
IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(BRD_REV_PAD_CTRL),
};
int board_gpio_init(void)
{
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
gpio_request(IMX_GPIO_NR(3, 5), "GPIO0");
gpio_direction_output(IMX_GPIO_NR(3, 5), 0); /*GPIO0*/
gpio_request(IMX_GPIO_NR(3, 15), "GPIO1");
gpio_direction_output(IMX_GPIO_NR(3, 15), 0); /*GPIO1*/
gpio_request(IMX_GPIO_NR(3, 17), "GPIO2");
gpio_direction_output(IMX_GPIO_NR(3, 17), 0); /*GPIO2*/
gpio_request(IMX_GPIO_NR(3, 18), "GPIO3");
gpio_direction_output(IMX_GPIO_NR(3, 18), 0); /*GPIO3*/
gpio_request(IMX_GPIO_NR(3, 16), "GPIO4");
gpio_direction_output(IMX_GPIO_NR(3, 16), 0); /*GPIO4*/
gpio_request(IMX_GPIO_NR(3, 10), "GPIO5");
gpio_direction_output(IMX_GPIO_NR(3, 10), 0); /*GPIO5*/
gpio_request(IMX_GPIO_NR(3, 11), "GPIO6");
gpio_direction_output(IMX_GPIO_NR(3, 11), 0); /*GPIO6*/
gpio_request(IMX_GPIO_NR(3, 12), "GPIO7");
gpio_direction_output(IMX_GPIO_NR(3, 12), 0); /*GPIO7*/
gpio_request(IMX_GPIO_NR(5, 6), "LVDS_VDD_EN");
gpio_direction_output(IMX_GPIO_NR(5, 6), 1); /*LVDS_VDD_EN*/
gpio_request(IMX_GPIO_NR(3, 20), "DSI_RST#");
gpio_direction_output(IMX_GPIO_NR(3, 20), 0); /*DSI_RST#*/
gpio_request(IMX_GPIO_NR(1, 5), "CAM_RST#");
gpio_direction_output(IMX_GPIO_NR(1, 5), 1); /*CAM0_RST#*/
gpio_request(IMX_GPIO_NR(1, 10), "GBE0_PWDN#");
gpio_direction_output(IMX_GPIO_NR(1, 10), 1); /*GBE0_PWDN*/
gpio_request(IMX_GPIO_NR(5, 0), "BRD_REV0");
gpio_direction_input(IMX_GPIO_NR(5, 0)); /* BRD_REV[0] */
gpio_request(IMX_GPIO_NR(5, 1), "BRD_REV1");
gpio_direction_input(IMX_GPIO_NR(5, 1)); /* BRD_REV[1] */
gpio_request(IMX_GPIO_NR(5, 2), "BRD_REV2");
gpio_direction_input(IMX_GPIO_NR(5, 2)); /* BRD_REV[2] */
return 0;
} }
int board_init(void) int board_init(void)
......
...@@ -13,6 +13,13 @@ enum boot_source ...@@ -13,6 +13,13 @@ enum boot_source
BOOT_SOURCE_SDHC, BOOT_SOURCE_SDHC,
}; };
struct pitx_gpio_t {
char *label; /* descriptive label */
int gpio; /* gpio pin number, e.g. IMX_GPIO_NR(1, 5) */
int inout; /* 0: input, 1: output */
int outval; /* initial output value */
};
static enum boot_source pitx_imx8m_boot_source(void); static enum boot_source pitx_imx8m_boot_source(void);
#endif #endif
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