Commit aaef53f1 authored by Thomas Schäfer's avatar Thomas Schäfer
Browse files

fsl: clean up DDR and MMC boot messages



- There are some boot messages during DDR and MMC initialization which
  are superfluous for normal boot. Convert them to debug messages.
Signed-off-by: Thomas Schäfer's avatarThomas Schaefer <thomas.schaefer@kontron.com>
parent 4cbcf8db
......@@ -95,7 +95,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
unsigned int tmp, initial_drate, target_freq;
int ret;
printf("DDRINFO: start DRAM init\n");
debug("DDRINFO: start DRAM init\n");
/* Step1: Follow the power up procedure */
if (is_imx8mq()) {
......@@ -118,7 +118,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
initial_drate = dram_timing->fsp_msg[0].drate;
/* default to the frequency point 0 clock */
printf("DDRINFO: DRAM rate %dMTS\n", initial_drate);
debug("DDRINFO: DRAM rate %dMTS\n", initial_drate);
ddrphy_init_set_dfi_clk(initial_drate);
/* D-aasert the presetn */
......@@ -185,7 +185,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
tmp = reg32_read(DDRPHY_CalBusy(0));
} while ((tmp & 0x1));
printf("DDRINFO:ddrphy calibration done\n");
debug("DDRINFO:ddrphy calibration done\n");
/* Step15: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
......@@ -240,7 +240,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
printf("DDRINFO: ddrmix config done\n");
debug("DDRINFO: ddrmix config done\n");
board_dram_ecc_scrub();
......
......@@ -515,7 +515,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
printf("Run CMD11 1.8V switch\n");
debug("Run CMD11 1.8V switch\n");
/* Sleep for 5 ms - max time for card to switch to 1.8V */
udelay(5000);
}
......
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