Commit 58e90168 authored by Thomas Schäfer's avatar Thomas Schäfer
Browse files

pitx-imx8m: fix UART RTS/CTS lines for rev2 and rev3 boards



- Due to an error in rev2 HW design, RTS/CTS of UART3 does not work. To
  prevent possible electrical damage, both lines are set up as GPIOs with
  appropriate settings. RTS/CTS flow control on UART3 is not available
  on rev2 modules.
- Add setup for UART3 RTS and CTS lines.
- Check hw revision and configure RTS/CTS as GPIO on rev2 modules.
Signed-off-by: Thomas Schäfer's avatarThomas Schaefer <thomas.schaefer@kontron.com>
parent 1e224850
......@@ -493,9 +493,6 @@ int board_mmc_get_env_dev(int devno)
#define TPM_RESET IMX_GPIO_NR(3, 2)
#define USBHUB_RESET IMX_GPIO_NR(3, 4)
#define IMX8MQ_PAD_ECSPI1_MISO__UART3_RTS_B IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, UART_PAD_CTRL)
#define IMX8MQ_PAD_ECSPI1_SS0__UART3_CTS_B IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, UART_PAD_CTRL)
int misc_init_r(void)
{
int hw_rev;
......@@ -533,8 +530,15 @@ int misc_init_r(void)
hw_rev = get_hw_rev();
/* check if hw variant is L120 (7) */
if (hw_rev == 7) {
imx_iomux_v3_setup_pad(IMX8MQ_PAD_ECSPI1_MISO__UART3_RTS_B);
imx_iomux_v3_setup_pad(IMX8MQ_PAD_ECSPI1_SS0__UART3_CTS_B);
imx_iomux_v3_setup_pad(IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 |
MUX_PAD_CTRL(UART_PAD_CTRL));
imx_iomux_v3_setup_pad(IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 |
MUX_PAD_CTRL(UART_PAD_CTRL | PAD_CTL_PUE));
gpio_request(IMX_GPIO_NR(5, 8), "UART3_CTS#");
gpio_direction_output(IMX_GPIO_NR(5, 8), 0);
gpio_request(IMX_GPIO_NR(5, 9), "UART3_RTS#");
gpio_direction_input(IMX_GPIO_NR(5, 9));
}
return 0;
......
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