pitx-imx8m: memory setup with derated parameters

- LPDDR4 manual de-rate workaround set to Option 2 for 4 GiB
  and 2 GiB memory variants.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>

board/kontron/pitx-imx8m/lpddr4_timing.c

@@ -18,19 +18,19 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400030, 0x1 },
 	{ 0x3d400000, 0xa3080020 },
 	{ 0x3d400028, 0x0 },
-	{ 0x3d400020, 0x203 },
+	{ 0x3d400020, 0x202 },
 	{ 0x3d400024, 0x3e800 },
-	{ 0x3d400064, 0x6100e0 },
+	{ 0x3d400064, 0x1800e0 },
 	{ 0x3d4000d0, 0xc003061c },
 	{ 0x3d4000d4, 0x9e0000 },
 	{ 0x3d4000dc, 0xd4002d },
 	{ 0x3d4000e0, 0x310008 },
 	{ 0x3d4000e8, 0x66004a },
 	{ 0x3d4000ec, 0x16004a },
-	{ 0x3d400100, 0x1a201b22 },
-	{ 0x3d400104, 0x60633 },
+	{ 0x3d400100, 0x1a200624 },
+	{ 0x3d400104, 0x60636 },
 	{ 0x3d40010c, 0xc0c000 },
-	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400110, 0x10040a10 },
 	{ 0x3d400114, 0x2040c0c },
 	{ 0x3d400118, 0x1010007 },
 	{ 0x3d40011c, 0x401 },
@@ -58,15 +58,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400204, 0x80808 },
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x7070707 },
-	{ 0x3d402020, 0x1 },
+	{ 0x3d402020, 0x0 },
 	{ 0x3d402024, 0x7d00 },
 	{ 0x3d402050, 0x20d040 },
-	{ 0x3d402064, 0xc001c },
+	{ 0x3d402064, 0x3001c },
 	{ 0x3d4020dc, 0x840000 },
 	{ 0x3d4020e0, 0x310000 },
 	{ 0x3d4020e8, 0x66004a },
 	{ 0x3d4020ec, 0x16004a },
-	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402100, 0xa040005 },
 	{ 0x3d402104, 0x30407 },
 	{ 0x3d402108, 0x203060b },
 	{ 0x3d40210c, 0x505000 },
@@ -82,7 +82,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d402190, 0x3818200 },
 	{ 0x3d402194, 0x80303 },
 	{ 0x3d4021b4, 0x100 },
-	{ 0x3d403020, 0x1 },
+	{ 0x3d403020, 0x0 },
 	{ 0x3d403024, 0x1f40 },
 	{ 0x3d403050, 0x20d040 },
 	{ 0x3d403064, 0x30007 },

board/kontron/pitx-imx8m/lpddr4_timing_2g.c

@@ -18,19 +18,19 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400030, 0x1 },
 	{ 0x3d400000, 0xa1080020 },
 	{ 0x3d400028, 0x0 },
-	{ 0x3d400020, 0x203 },
+	{ 0x3d400020, 0x202 },
 	{ 0x3d400024, 0x3e800 },
-	{ 0x3d400064, 0x6100e0 },
+	{ 0x3d400064, 0x1800e0 },
 	{ 0x3d4000d0, 0xc003061c },
 	{ 0x3d4000d4, 0x9e0000 },
 	{ 0x3d4000dc, 0xd4002d },
 	{ 0x3d4000e0, 0x310008 },
 	{ 0x3d4000e8, 0x66004a },
 	{ 0x3d4000ec, 0x16004a },
-	{ 0x3d400100, 0x1a201b22 },
-	{ 0x3d400104, 0x60633 },
+	{ 0x3d400100, 0x1a200624 },
+	{ 0x3d400104, 0x60636 },
 	{ 0x3d40010c, 0xc0c000 },
-	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400110, 0x10040a10 },
 	{ 0x3d400114, 0x2040c0c },
 	{ 0x3d400118, 0x1010007 },
 	{ 0x3d40011c, 0x401 },
@@ -58,15 +58,15 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400204, 0x80808 },
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x7070707 },
-	{ 0x3d402020, 0x1 },
+	{ 0x3d402020, 0x0 },
 	{ 0x3d402024, 0x7d00 },
 	{ 0x3d402050, 0x20d040 },
-	{ 0x3d402064, 0xc001c },
+	{ 0x3d402064, 0x3001c },
 	{ 0x3d4020dc, 0x840000 },
 	{ 0x3d4020e0, 0x310000 },
 	{ 0x3d4020e8, 0x66004a },
 	{ 0x3d4020ec, 0x16004a },
-	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402100, 0xa040005 },
 	{ 0x3d402104, 0x30407 },
 	{ 0x3d402108, 0x203060b },
 	{ 0x3d40210c, 0x505000 },
@@ -82,7 +82,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d402190, 0x3818200 },
 	{ 0x3d402194, 0x80303 },
 	{ 0x3d4021b4, 0x100 },
-	{ 0x3d403020, 0x1 },
+	{ 0x3d403020, 0x0 },
 	{ 0x3d403024, 0x1f40 },
 	{ 0x3d403050, 0x20d040 },
 	{ 0x3d403064, 0x30007 },