Commit 150c94b5 authored by Thomas Schäfer's avatar Thomas Schäfer
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ARM: IMX8M: introduce support for dynamic memory variants



- Current implementation requires that memory size is configured using
  PHYS_SDRAM and PHYS_SDRAM_2 settings depending on actual memory
  size in the board config file. As PHYS_SDRAM_2 memory area is not
  used if total memory size is < 3 GiB, cache and MMU setup would use
  wrong values when initialized. Thus, dynamic initialization of 4 GiB
  and 2 GiB modules is not possible with one single bootloader binary.
- Add support to determine actual memory size using the
  'board_phys_sdram_size' function and calculate size of DRAM1 and
  DRAM2 regions accordingly. Fix cache enable setup to use detected size
  of memory areas instead of fixed config values.
- Ensure that memory regions are set up properly even if OPTEE memory
  region splits DRAM1 into multiple regions.
Signed-off-by: Thomas Schäfer's avatarThomas Schaefer <thomas.schaefer@kontron.com>
parent b66b948b
...@@ -131,32 +131,20 @@ static struct mm_region imx8m_mem_map[] = { ...@@ -131,32 +131,20 @@ static struct mm_region imx8m_mem_map[] = {
PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, { }, {
/* DRAM1 */ /* DRAM1 */
.virt = 0x40000000UL, /*
.phys = 0x40000000UL, * Initialize DRAM1 and DRAM2 entries as empty and fill
.size = PHYS_SDRAM_SIZE, * them with appropriate values when 'enable_caches' is
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | * executed.
#ifdef CONFIG_IMX_TRUSTY_OS * Additional entries are reserved in case that TEEs are
PTE_BLOCK_INNER_SHARE * used which means that DRAM entries can be split up
#else * further.
PTE_BLOCK_OUTER_SHARE */
#endif 0,
#ifdef PHYS_SDRAM_2_SIZE
}, { }, {
/* DRAM2 */ /* DRAM2 */
.virt = 0x100000000UL, 0,
.phys = 0x100000000UL,
.size = PHYS_SDRAM_2_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#ifdef CONFIG_IMX_TRUSTY_OS
PTE_BLOCK_INNER_SHARE
#else
PTE_BLOCK_OUTER_SHARE
#endif
#endif
}, { }, {
/* empty entrie to split table entry 5 /* reserved for additional entries due to TEE */
* if needed when TEEs are used
*/
0, 0,
}, { }, {
/* List terminator */ /* List terminator */
...@@ -168,29 +156,32 @@ struct mm_region *mem_map = imx8m_mem_map; ...@@ -168,29 +156,32 @@ struct mm_region *mem_map = imx8m_mem_map;
void enable_caches(void) void enable_caches(void)
{ {
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */ /*
if (rom_pointer[1]) { * If OPTEE runs, remove OPTEE memory from MMU table to avoid
* speculative prefetch.
/* TEE are loaded, So the ddr bank structures */
* have been modified update mmu table accordingly int i = 0;
*/ /*
int i = 0; * please make sure that entry initial value matches
/* please make sure that entry initial value matches * imx8m_mem_map for DRAM1
* imx8m_mem_map for DRAM1 */
*/ int entry = 5;
int entry = 5; u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
u64 attrs = imx8m_mem_map[entry].attrs; #ifdef CONFIG_IMX_TRUSTY_OS
while (i < CONFIG_NR_DRAM_BANKS && entry < 8) { PTE_BLOCK_INNER_SHARE;
if (gd->bd->bi_dram[i].start == 0) #else
break; PTE_BLOCK_OUTER_SHARE;
imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; #endif
imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; if (gd->bd->bi_dram[i].start == 0)
imx8m_mem_map[entry].attrs = attrs; break;
debug("Added memory mapping (%d): %llx %llx\n", entry, imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
i++;entry++; imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
} imx8m_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
i++;entry++;
} }
icache_enable(); icache_enable();
...@@ -233,17 +224,27 @@ int dram_init_banksize(void) ...@@ -233,17 +224,27 @@ int dram_init_banksize(void)
int bank = 0; int bank = 0;
int ret; int ret;
phys_size_t sdram_size; phys_size_t sdram_size;
#ifndef PHYS_SDRAM_2_SIZE
phys_size_t sdram2_size = 0x0ULL;
#endif
ret = board_phys_sdram_size(&sdram_size); ret = board_phys_sdram_size(&sdram_size);
if (ret) if (ret)
return ret; return ret;
#ifndef PHYS_SDRAM_2_SIZE
if (sdram_size > PHYS_SDRAM_SIZE) {
sdram2_size = sdram_size - PHYS_SDRAM_SIZE;
sdram_size = PHYS_SDRAM_SIZE;
}
#endif
gd->bd->bi_dram[bank].start = PHYS_SDRAM; gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) { if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1]; phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start -gd->bd->bi_dram[bank].start; gd->bd->bi_dram[bank].size = optee_start -
gd->bd->bi_dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
if ( ++bank >= CONFIG_NR_DRAM_BANKS) { if ( ++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n"); puts("CONFIG_NR_DRAM_BANKS is not enough\n");
...@@ -258,13 +259,19 @@ int dram_init_banksize(void) ...@@ -258,13 +259,19 @@ int dram_init_banksize(void)
gd->bd->bi_dram[bank].size = sdram_size; gd->bd->bi_dram[bank].size = sdram_size;
} }
#ifndef PHYS_SDRAM_2_SIZE
if (sdram2_size) {
#endif
if ( ++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is too small for SDRAM_2\n");
return -1;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
#ifdef PHYS_SDRAM_2_SIZE #ifdef PHYS_SDRAM_2_SIZE
if ( ++bank >= CONFIG_NR_DRAM_BANKS) { gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); #else
return -1; gd->bd->bi_dram[bank].size = sdram2_size;
} }
gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
#endif #endif
return 0; return 0;
......
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