pitx-imx8mq.dts 11.2 KB
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// SPDX-License-Identifier: GPL-2.0+
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/*
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 * (C) Copyright 2019
 *     Kontron Asia Pacific Design
 * (C) Copyright 2020
 *     Thomas Schaefer, Kontron Europe GmbH
 *     thomas.schaefer@kontron.com
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 */

/dts-v1/;

/* First 128KB is for PSCI ATF. */
/memreserve/ 0x40000000 0x00020000;

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#include "imx8mq.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "Kontron pITX-iMX8M";
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	compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
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	chosen {
		bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200";
		stdout-path = &uart3;
	};

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	reg_usdhc2_vmmc: regulator-vsd-3v3 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2>;
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		// off-on-delay-us = <20000>;
		enable-active-high;
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	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
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	phy-reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
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	fsl,magic-packet;
	status = "okay";

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	/* START of DP83867 patch for U-Boot */
	/*
	 * For some unknown reasons, DP83867 PHY driver for U-Boot doesn't
	 * read its properties from the phy0 node.
	 * As a workaround, we move them here
	 */
	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
	ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	ti,dp83867-rxctrl-strap-quirk = <1>;
	/* END of DP83867 patch for U-Boot */

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	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
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			compatible = "ti,dp83867", "ethernet-phy-ieee802.3-c22";
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			reg = <0>;
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			// ti,min-output-impedance;
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		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

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	pmic@8 {
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		compatible = "fsl,pfuze100";
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		fsl,pfuze-support-disable-sw;
		reg = <0x8>;
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		regulators {
			sw1a_reg: sw1ab {
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				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
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			};

			sw1c_reg: sw1c {
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				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
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			};

			sw2_reg: sw2 {
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				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
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				regulator-always-on;
			};

			sw3a_reg: sw3ab {
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				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
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				regulator-always-on;
			};

			sw4_reg: sw4 {
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				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
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				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
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				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <975000>;
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				regulator-always-on;
			};

			vgen3_reg: vgen3 {
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				regulator-min-microvolt = <1675000>;
				regulator-max-microvolt = <1975000>;
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				regulator-always-on;
			};

			vgen4_reg: vgen4 {
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				regulator-min-microvolt = <1625000>;
				regulator-max-microvolt = <1875000>;
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				regulator-always-on;
			};

			vgen5_reg: vgen5 {
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				regulator-min-microvolt = <3075000>;
				regulator-max-microvolt = <3625000>;
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				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

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&pgc_gpu {
	power-supply = <&sw1a_reg>;
};

&snvs_pwrkey {
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	status = "okay";
};

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&qspi0 {
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	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

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	flash0: mx25l12835f@0 {
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		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
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		compatible = "jedec,spi-nor";
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		spi-max-frequency = <20000000>;
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		spi-tx-bus-width = <2>;
		spi-rx-bus-width = <2>;
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	};
};

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&uart3 {
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	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
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	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
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	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb_dwc3_0 {
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	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	snps,dis-u1-entry-quirk;
	snps,dis-u2-entry-quirk;
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	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

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&usb_dwc3_1 {
	dr_mode = "host";
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	status = "okay";
};

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&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vqmmc-supply = <&sw4_reg>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	mmc-hs400-1_8v;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	status = "okay";
};

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&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};
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&dcss {
	status = "okay";
	port@0 {
		dcss_out: endpoint {
			remote-endpoint = <&hdmi_in>;
		};
	};
};

&hdmi {
	compatible = "fsl,imx8mq-hdmi";
	status = "okay";

	display-timings {
		native-mode = <&timing1>;

		timing1: timing1 {
			clock-frequency = <74250000>;
			hactive = <1280>;
			vactive = <720>;
			hfront-porch = <220>;
			hback-porch = <110>;
			hsync-len = <40>;
			vback-porch = <5>;
			vfront-porch = <20>;
			vsync-len = <5>;
		};
	};

	port@0 {
		hdmi_in: endpoint {
			remote-endpoint = <&dcss_out>;
		};
	};
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
		>;
	};

	/* PCIE0 for M.2 */
	pinctrl_m2: m2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x16	/* PCIE_PERST# */
			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x16	/* W_DISABLE# */
		>;
	};

	/* PCIE1 for GbE I210 */
	pinctrl_i210: i210grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x16 /* PCIE_PERST# */
		>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x82
			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82
			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82
			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82
			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82
			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82

		>;
	};

	pinctrl_reg_usdhc2: regusdhc2grpgpio {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79
			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79
			MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x79
			MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x79
			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19
		>;
	};



	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_wdog: wdog1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};
};